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OpenForge Foundation IP

The IP portfolio

The OFIP catalog plans foundation IP for radar, RF, LiDAR, infrared, AI, GPU, TPU, quantum control, automotive and the data centre. Digital blocks target both FPGA fabric and CMOS ASICs. Every ASIC-only block names the route an FPGA design takes instead. Every block has its own datasheet page.

Catalogued 1,410Implemented 271FPGA-routed 26Categories 13Families 213

Explorer

Pick a corner of the die

Each area is drawn to scale by entry count. Select one to zoom into its families, stack the filters, then open any block for its pinout and datasheet.

die: OFIP · 13 blocks · area ∝ entriesbar: share implemented
Category
Maturity
Target
Loading the catalogSelect a card for its pinout and datasheet

Targets

Where each block can be built

The target follows from what the block is. Digital RTL synthesizes to FPGA fabric and to a CMOS ASIC. Analog, mixed-signal, PHY and physical IP needs transistor-level design and silicon proof.

1,007

FPGA and ASIC

Digital blocks that synthesize to FPGA fabric and to standard cells on a CMOS process.

321

ASIC (CMOS) only

Analog, PHY and physical blocks. Each names its FPGA route, such as transceiver hard IP or an external part.

82

III-V process

Blocks for compound-semiconductor processes such as GaAs and InP, for RF, optical and high-speed front ends.

The quality bar for an implemented block

A block is only marked implemented when all of these hold. Tiers above simulated add the flows on the technology page.

  • Original or permissive basisOriginal RTL, or a permissive project recorded as its basis with licence headers kept. No copyleft code in a block.
  • Lint cleanClean under verilator -Wall before anything else runs.
  • Self-checking testbenchChecked against a bit-exact Python reference model, with official vectors where they exist (NIST CAVP, RFCs, IEEE tables).
  • Mutation checkedInjected bugs must make the testbench fail, so a passing test means something.
  • Formal where it fitsProperties for arbiters, FIFOs, protocol checkers and other blocks whose correctness is a state property.
  • SynthesizedYosys synthesis with area and delay reported, and an honest verification status in the component file.

Start integrating before a block exists

Every catalog entry, planned or built, generates a lint-clean skeleton with its ports, control bus and ID, VERSION and STATUS registers, so SoC integration and firmware can start on day one.

# list, count and generate openforge ip catalog list --category processors openforge ip catalog stats openforge ip catalog skeleton of_uart -o build/ip

Use OFIP, or build it with us

IP integrators and SoC teams can pull blocks early, contribute blocks and verification IP, or plan shuttle test chips with us.

Join the program