IP PortfolioDatapath and DSP
Foundation datapath and DSP building blocks
Arithmetic, floating point, number formats, CRC/ECC, FIFOs and memories wrappers, arbiters, counters, DSP primitives (FIR, IIR, FFT, CORDIC, NCO), compression and encoding blocks.
Blocks 147Implemented 78Families 16FPGA + ASIC 147
integer arithmetic 33floating point 14bit manipulation 7code conversion 4error control coding 12control and scheduling 14random number generation 4storage helpers 14number theory 4encoding and line coding 8compression 5dsp filters 7dsp transforms and oscillators 6dsp signal processing 7sorting and selection 3matrix and linear algebra 5
integer arithmetic
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_add_ripple | Ripple-carry adder | simulated | FPGA + ASIC | Easy |
| of_add_cla | Carry-lookahead adder | simulated | FPGA + ASIC | Easy |
| of_add_csel | Carry-select adder | simulated | FPGA + ASIC | Easy |
| of_add_kogge_stone | Kogge-Stone parallel-prefix adder | fpga-routed | FPGA + ASIC | Easy |
| of_add_brent_kung | Brent-Kung parallel-prefix adder | simulated | FPGA + ASIC | Easy |
| of_add_sklansky | Sklansky parallel-prefix adder | simulated | FPGA + ASIC | Easy |
| of_addsub | Adder/subtractor with flags | simulated | FPGA + ASIC | Easy |
| of_inc | Incrementer / decrementer | simulated | FPGA + ASIC | Easy |
| of_abs | Absolute value | simulated | FPGA + ASIC | Easy |
| of_cmp | Magnitude comparator | simulated | FPGA + ASIC | Easy |
| of_minmax | N-input min/max with index | simulated | FPGA + ASIC | Easy |
| of_sat_addsub | Saturating adder/subtractor | simulated | FPGA + ASIC | Easy |
| of_csa_tree | Carry-save adder tree (Wallace / Dadda) | simulated | FPGA + ASIC | Medium |
| of_multp | Partial-product multiplier (carry-save output) | simulated | FPGA + ASIC | Medium |
| of_mul_array | Array multiplier | simulated | FPGA + ASIC | Easy |
| of_mul_booth4 | Radix-4 Booth multiplier | fpga-routed | FPGA + ASIC | Medium |
| of_mul_wallace | Wallace-tree multiplier | simulated | FPGA + ASIC | Medium |
| of_mul_dadda | Dadda-tree multiplier | simulated | FPGA + ASIC | Medium |
| of_mul_pipe | Pipelined multiplier | simulated | FPGA + ASIC | Medium |
| of_mac | Multiply-accumulate unit | simulated | FPGA + ASIC | Medium |
| of_div_seq | Sequential divider (restoring / non-restoring) | fpga-routed | FPGA + ASIC | Medium |
| of_div_pipe | Pipelined array divider | simulated | FPGA + ASIC | Medium |
| of_sqrt | Integer square root | simulated | FPGA + ASIC | Medium |
| of_requant | Fixed-point requantizer (round + saturate) | simulated | FPGA + ASIC | Easy |
| of_mul_seq | Sequential shift-add multiplier | planned | FPGA + ASIC | Easy |
| of_mul_karatsuba | Karatsuba wide-operand multiplier | planned | FPGA + ASIC | Hard |
| of_div_srt | Radix-4 SRT divider | planned | FPGA + ASIC | Hard |
| of_div_const | Divide-by-constant unit | planned | FPGA + ASIC | Easy |
| of_int_alu | Integer ALU | simulated | FPGA + ASIC | Easy |
| of_dotp_int | Integer dot-product unit (INT8/INT4) | simulated | FPGA + ASIC | Medium |
| of_recip_nr | Fixed-point reciprocal and reciprocal square root | planned | FPGA + ASIC | Medium |
| of_log_exp | Fixed-point log2 and exp2 unit | planned | FPGA + ASIC | Medium |
| of_pwl_func | Piecewise-linear function approximator | planned | FPGA + ASIC | Easy |
floating point
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_fp_add | Floating-point adder/subtractor | simulated | FPGA + ASIC | Medium |
| of_fp_mul | Floating-point multiplier | simulated | FPGA + ASIC | Medium |
| of_fp_round | Floating-point round & pack unit | simulated | FPGA + ASIC | Medium |
| of_fp2int | Floating-point to fixed-point converter | simulated | FPGA + ASIC | Medium |
| of_int2fp | Fixed-point to floating-point converter | simulated | FPGA + ASIC | Medium |
| of_fp_fma | Floating-point fused multiply-add | simulated | FPGA + ASIC | Hard |
| of_fp_divsqrt | Floating-point divide and square root | simulated | FPGA + ASIC | Hard |
| of_fp_cmp | Floating-point compare, min/max and classify | simulated | FPGA + ASIC | Easy |
| of_fp_cvt | Floating-point format converter | simulated | FPGA + ASIC | Medium |
| of_bf16_dotp | bfloat16 dot-product unit | simulated | FPGA + ASIC | Medium |
| of_fp8_mac | FP8 (E4M3 / E5M2) multiply-accumulate | simulated | FPGA + ASIC | Medium |
| of_mx_quant | Microscaling (MX) block quantizer | planned | FPGA + ASIC | Medium |
| of_posit_unit | Posit arithmetic unit | planned | FPGA + ASIC | Hard |
| of_fp_transc | Floating-point transcendental unit | planned | FPGA + ASIC | Hard |
bit manipulation
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_lzc | Leading-zero / leading-one counter | fpga-routed | FPGA + ASIC | Easy |
| of_popcount | Population count | simulated | FPGA + ASIC | Easy |
| of_prienc | Priority encoder | simulated | FPGA + ASIC | Easy |
| of_shifter | Barrel shifter / rotator | simulated | FPGA + ASIC | Easy |
| of_bitrev | Bit, byte and nibble reverse / swap | planned | FPGA + ASIC | Easy |
| of_bitmanip_rv | RISC-V bit-manipulation unit | planned | FPGA + ASIC | Medium |
| of_clmul | Carry-less multiplier | planned | FPGA + ASIC | Easy |
code conversion
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_bin2gray | Binary to Gray converter | fpga-routed | FPGA + ASIC | Easy |
| of_gray2bin | Gray to binary converter | simulated | FPGA + ASIC | Easy |
| of_bin2onehot | Binary to one-hot decoder | simulated | FPGA + ASIC | Easy |
| of_onehot2bin | One-hot to binary encoder | simulated | FPGA + ASIC | Easy |
error control coding
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_crc | Parallel CRC | fpga-routed | FPGA + ASIC | Easy |
| of_ecc_enc | Hamming / SECDED encoder | simulated | FPGA + ASIC | Easy |
| of_ecc_dec | Hamming / SECDED decoder | simulated | FPGA + ASIC | Easy |
| of_parity | Parity generator and checker | planned | FPGA + ASIC | Easy |
| of_bch_codec | BCH encoder and decoder | planned | FPGA + ASIC | Hard |
| of_rs_codec | Reed-Solomon encoder and decoder | planned | FPGA + ASIC | Hard |
| of_ldpc_dec | LDPC encoder and decoder | planned | FPGA + ASIC | Very hard |
| of_polar_codec | Polar encoder and list decoder | planned | FPGA + ASIC | Very hard |
| of_turbo_dec | Turbo encoder and decoder | planned | FPGA + ASIC | Very hard |
| of_viterbi | Convolutional encoder and Viterbi decoder | planned | FPGA + ASIC | Medium |
| of_ecc_symbol | Symbol-based memory ECC (single symbol correct) | planned | FPGA + ASIC | Hard |
| of_interleaver | Block and convolutional interleaver | planned | FPGA + ASIC | Easy |
control and scheduling
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_cnt_updown | Up/down counter | simulated | FPGA + ASIC | Easy |
| of_cnt_gray | Gray-code counter | simulated | FPGA + ASIC | Easy |
| of_cnt_johnson | Johnson counter | simulated | FPGA + ASIC | Easy |
| of_arb_fixed | Fixed-priority arbiter | simulated | FPGA + ASIC | Easy |
| of_arb_rr | Round-robin arbiter | fpga-routed | FPGA + ASIC | Easy |
| of_arb_wrr | Weighted round-robin arbiter | simulated | FPGA + ASIC | Easy |
| of_arb_matrix | Matrix (least-recently-granted) arbiter | simulated | FPGA + ASIC | Easy |
| of_credit_cnt | Credit counter | simulated | FPGA + ASIC | Easy |
| of_debounce | Debouncer | simulated | FPGA + ASIC | Easy |
| of_edge_detect | Edge detector | simulated | FPGA + ASIC | Easy |
| of_oneshot | One-shot (monostable) pulse generator | simulated | FPGA + ASIC | Easy |
| of_pwm | Multi-channel PWM generator | fpga-routed | FPGA + ASIC | Easy |
| of_sched_dwrr | Deficit weighted round-robin scheduler | planned | FPGA + ASIC | Medium |
| of_token_bucket | Token bucket rate limiter | planned | FPGA + ASIC | Easy |
random number generation
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_lfsr | LFSR (Fibonacci / Galois) | simulated | FPGA + ASIC | Easy |
| of_prbs | PRBS generator and checker | simulated | FPGA + ASIC | Easy |
| of_xoshiro | xoshiro / xoroshiro PRNG | planned | FPGA + ASIC | Easy |
| of_awgn | Gaussian noise generator | planned | FPGA + ASIC | Medium |
storage helpers
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_fifo_sync | Synchronous FIFO | fpga-routed | FPGA + ASIC | Easy |
| of_fifo_async | Asynchronous (dual-clock) FIFO | simulated | FPGA + ASIC | Medium |
| of_lifo | Synchronous stack (LIFO) | simulated | FPGA + ASIC | Easy |
| of_regfile | Multi-port register file | simulated | FPGA + ASIC | Easy |
| of_cam | Content-addressable memory (flop-based) | fpga-routed | FPGA + ASIC | Medium |
| of_delay_line | Shift-register delay line | simulated | FPGA + ASIC | Easy |
| of_tcam | Ternary CAM (logic based) | planned | FPGA + ASIC | Medium |
| of_pingpong | Ping-pong (double) buffer | planned | FPGA + ASIC | Easy |
| of_line_buffer | Image line buffer | planned | FPGA + ASIC | Easy |
| of_fifo_packet | Packet FIFO with commit and drop | simulated | FPGA + ASIC | Medium |
| of_queue_mgr | Multi-queue shared buffer manager | planned | FPGA + ASIC | Hard |
| of_ram_wrap | Generic RAM wrapper | simulated | FPGA + ASIC | Easy |
| of_rob | Reorder buffer | planned | FPGA + ASIC | Medium |
| of_hash_lookup | Hash table lookup engine | planned | FPGA + ASIC | Hard |
number theory
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_mod_addsub | Modular adder and subtractor | planned | FPGA + ASIC | Easy |
| of_mont_mul | Montgomery modular multiplier | planned | FPGA + ASIC | Hard |
| of_barrett_red | Barrett modular reducer | planned | FPGA + ASIC | Medium |
| of_ntt_butterfly | Number-theoretic transform butterfly and engine | planned | FPGA + ASIC | Hard |
encoding and line coding
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_enc_8b10b | 8b/10b encoder and decoder | simulated | FPGA + ASIC | Easy |
| of_enc_64b66b | 64b/66b encoder, decoder and block lock | simulated | FPGA + ASIC | Medium |
| of_enc_128b130b | 128b/130b encoder and decoder | planned | FPGA + ASIC | Medium |
| of_scrambler | Scrambler and descrambler family | planned | FPGA + ASIC | Easy |
| of_enc_manchester | Manchester and differential Manchester codec | planned | FPGA + ASIC | Easy |
| of_enc_nrzi_stuff | NRZI and bit-stuffing codec | planned | FPGA + ASIC | Easy |
| of_enc_4b5b_mlt3 | 4B/5B and MLT-3 line coder | planned | FPGA + ASIC | Easy |
| of_checksum | Internet, Fletcher and Adler checksum engine | planned | FPGA + ASIC | Easy |
compression
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_huffman_dec | Canonical Huffman decoder | planned | FPGA + ASIC | Medium |
| of_deflate_dec | DEFLATE / gzip / zlib decompressor | planned | FPGA + ASIC | Hard |
| of_deflate_enc | DEFLATE / gzip compressor | planned | FPGA + ASIC | Very hard |
| of_lz4_codec | LZ4 compressor and decompressor | planned | FPGA + ASIC | Hard |
| of_zstd_dec | Zstandard decompressor | planned | FPGA + ASIC | Very hard |
dsp filters
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_fir | FIR filter | simulated | FPGA + ASIC | Medium |
| of_fir_polyphase | Polyphase decimator and interpolator | simulated | FPGA + ASIC | Medium |
| of_cic | CIC decimator and interpolator | simulated | FPGA + ASIC | Easy |
| of_halfband | Half-band filter | planned | FPGA + ASIC | Easy |
| of_iir_biquad | IIR biquad cascade | planned | FPGA + ASIC | Medium |
| of_farrow | Fractional resampler (Farrow) | planned | FPGA + ASIC | Medium |
| of_lms | Adaptive LMS / NLMS filter | planned | FPGA + ASIC | Medium |
dsp transforms and oscillators
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_fft_stream | Streaming pipelined FFT/IFFT | planned | FPGA + ASIC | Hard |
| of_fft_mem | Memory-based mixed-radix FFT | planned | FPGA + ASIC | Hard |
| of_cordic | CORDIC rotator and vectoring unit | fpga-routed | FPGA + ASIC | Medium |
| of_nco | NCO / direct digital synthesizer | simulated | FPGA + ASIC | Easy |
| of_window | Window function generator | planned | FPGA + ASIC | Easy |
| of_dct | 2D DCT / IDCT | planned | FPGA + ASIC | Medium |
dsp signal processing
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_cmul | Complex multiplier | simulated | FPGA + ASIC | Easy |
| of_mixer | Digital complex mixer | planned | FPGA + ASIC | Easy |
| of_ddc | Digital down-converter | planned | FPGA + ASIC | Hard |
| of_duc | Digital up-converter | planned | FPGA + ASIC | Hard |
| of_correlator | Multi-lag correlator | planned | FPGA + ASIC | Medium |
| of_matched_filter | Matched filter and pulse compressor | planned | FPGA + ASIC | Hard |
| of_agc | Digital automatic gain control | planned | FPGA + ASIC | Easy |
sorting and selection
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_sort_network | Sorting network generator | planned | FPGA + ASIC | Medium |
| of_merge_sort | Streaming merge sorter | planned | FPGA + ASIC | Hard |
| of_topk | Top-K selector | planned | FPGA + ASIC | Medium |
matrix and linear algebra
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_systolic_mm | Systolic matrix multiply array | planned | FPGA + ASIC | Hard |
| of_transpose | Matrix transpose and corner-turn buffer | planned | FPGA + ASIC | Medium |
| of_qr_givens | QR decomposition (Givens rotations) | planned | FPGA + ASIC | Hard |
| of_cholesky | Cholesky decomposition and solver | planned | FPGA + ASIC | Hard |
| of_mat_inv | Matrix inversion unit | planned | FPGA + ASIC | Hard |