IP PortfolioInterface controllers

Interface controllers (digital)

Protocol controllers and MACs for every external interface: low-speed serial, memory, storage, networking, USB, PCIe/CXL, display, camera, automotive, industrial and chiplet links.

Blocks 148Implemented 17Families 45FPGA + ASIC 148

uart

3 blocks · 2 implemented

ID	Block	Maturity	Targets	Difficulty
of_uart	UART with APB interface	fpga-routed	FPGA + ASIC	Easy
of_uart_16550	16550-compatible UART	simulated	FPGA + ASIC	Easy
of_usart	USART with RS-485 and IrDA SIR	planned	FPGA + ASIC	Medium

i2c

4 blocks · 3 implemented

ID	Block	Maturity	Targets	Difficulty
of_i2c_master	I2C master	fpga-routed	FPGA + ASIC	Easy
of_i2c_slave	I2C slave	simulated	FPGA + ASIC	Easy
of_i2c_multimaster	I2C multi-master controller	simulated	FPGA + ASIC	Medium
of_smbus_pmbus	SMBus/PMBus controller	planned	FPGA + ASIC	Medium

i3c

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_i3c_controller	MIPI I3C controller	planned	FPGA + ASIC	Hard
of_i3c_target	MIPI I3C target	planned	FPGA + ASIC	Medium

spi

2 blocks · 2 implemented

ID	Block	Maturity	Targets	Difficulty
of_spi_master	SPI master	fpga-routed	FPGA + ASIC	Easy
of_spi_slave	SPI slave	simulated	FPGA + ASIC	Easy

spi_flash

2 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_qspi_flash	Quad SPI NOR flash controller	simulated	FPGA + ASIC	Medium
of_xspi_octal	Octal SPI / xSPI controller	planned	FPGA + ASIC	Hard

low_speed

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_onewire	1-Wire master	planned	FPGA + ASIC	Easy

gpio

1 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_gpio	GPIO controller	fpga-routed	FPGA + ASIC	Easy

pwm

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_pwm_motor	Motor-control PWM	planned	FPGA + ASIC	Medium

audio

4 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_i2s_tdm	I2S / TDM audio port	simulated	FPGA + ASIC	Easy
of_pdm_mic	PDM microphone interface	planned	FPGA + ASIC	Medium
of_soundwire	MIPI SoundWire manager	planned	FPGA + ASIC	Hard
of_spdif	S/PDIF transmitter and receiver	planned	FPGA + ASIC	Easy

can

3 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_can20	CAN 2.0 controller	simulated	FPGA + ASIC	Medium
of_canfd	CAN FD controller	planned	FPGA + ASIC	Hard
of_canxl	CAN XL controller	planned	FPGA + ASIC	Hard

lin

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_lin	LIN commander/responder	planned	FPGA + ASIC	Easy

flexray

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_flexray	FlexRay communication controller	planned	FPGA + ASIC	Hard

sensor_bus

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sent	SENT receiver	planned	FPGA + ASIC	Easy
of_psi5	PSI5 receiver	planned	FPGA + ASIC	Medium

auto_ethernet

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_eth_auto_mac	Automotive Ethernet MAC	planned	FPGA + ASIC	Medium
of_eth_t1s_mac	10BASE-T1S MAC with PLCA	planned	FPGA + ASIC	Medium

industrial_ethernet

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_ethercat_sub	EtherCAT SubDevice controller	planned	FPGA + ASIC	Hard
of_profinet_irt	PROFINET IRT device switch	planned	FPGA + ASIC	Very hard

fieldbus

5 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_modbus_rtu	Modbus RTU/ASCII framer	planned	FPGA + ASIC	Easy
of_iolink_master	IO-Link master port	planned	FPGA + ASIC	Medium
of_iolink_device	IO-Link device	planned	FPGA + ASIC	Medium
of_dali	DALI-2 lighting control interface	planned	FPGA + ASIC	Easy
of_encoder_ssi_biss	SSI and BiSS-C encoder master	planned	FPGA + ASIC	Easy

tsn

5 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_tsn_gptp	gPTP time synchronisation unit	simulated	FPGA + ASIC	Medium
of_tsn_qbv	Time-aware shaper (802.1Qbv)	planned	FPGA + ASIC	Medium
of_tsn_qbu	Frame preemption (802.1Qbu/802.3br)	planned	FPGA + ASIC	Hard
of_tsn_frer	Frame replication and elimination (802.1CB)	planned	FPGA + ASIC	Hard
of_tsn_switch	TSN Ethernet switch	planned	FPGA + ASIC	Very hard

dram

9 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_ddr3_ctrl	DDR3/DDR3L memory controller	planned	FPGA + ASIC	Hard
of_ddr4_ctrl	DDR4 memory controller	planned	FPGA + ASIC	Hard
of_ddr5_ctrl	DDR5 memory controller	planned	FPGA + ASIC	Very hard
of_ddr5_mrdimm_ctrl	DDR5 MRDIMM host controller	planned	FPGA + ASIC	Very hard
of_lpddr4_ctrl	LPDDR4/LPDDR4X memory controller	planned	FPGA + ASIC	Hard
of_lpddr5_ctrl	LPDDR5/LPDDR5X memory controller	planned	FPGA + ASIC	Very hard
of_lpddr6_ctrl	LPDDR6 memory controller	planned	FPGA + ASIC	Very hard
of_gddr6_ctrl	GDDR6 memory controller	planned	FPGA + ASIC	Very hard
of_gddr7_ctrl	GDDR7 memory controller	planned	FPGA + ASIC	Very hard

hbm

3 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_hbm2e_ctrl	HBM2E memory controller	planned	FPGA + ASIC	Very hard
of_hbm3_ctrl	HBM3/HBM3E memory controller	planned	FPGA + ASIC	Very hard
of_hbm4_ctrl	HBM4 memory controller	planned	FPGA + ASIC	Very hard

sram

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_qdr_sram_ctrl	QDR-II+/QDR-IV SRAM controller	planned	FPGA + ASIC	Medium
of_static_mem_ctrl	Static memory controller (SRAM/NOR/PSRAM)	planned	FPGA + ASIC	Easy

psram

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_hyperbus	HyperBus controller	planned	FPGA + ASIC	Medium

nand

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_nand_ctrl	NAND flash controller (ONFI/Toggle)	planned	FPGA + ASIC	Hard

sd_mmc

3 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_sd_host	SD/SDIO host controller	simulated	FPGA + ASIC	Medium
of_emmc_host	eMMC 5.1 host controller	planned	FPGA + ASIC	Medium
of_sdio_device	SDIO device controller	planned	FPGA + ASIC	Medium

ufs

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_ufs_host	UFS 4.0 host controller with UniPro	planned	FPGA + ASIC	Very hard
of_ufs_device	UFS device controller	planned	FPGA + ASIC	Very hard

sata

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sata_host	SATA host controller (AHCI)	planned	FPGA + ASIC	Hard

nvme

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_nvme_host	NVMe host initiator	planned	FPGA + ASIC	Hard
of_nvme_target	NVMe device controller	planned	FPGA + ASIC	Very hard

sas

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sas_ctrl	SAS-4 link and port layer	planned	FPGA + ASIC	Very hard

ethernet_mac

6 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_eth_mac_1g	1G Ethernet MAC	simulated	FPGA + ASIC	Medium
of_eth_mac_10g	10G Ethernet MAC and 10GBASE-R PCS	planned	FPGA + ASIC	Medium
of_eth_mac_25g	25G Ethernet MAC, PCS and RS-FEC	planned	FPGA + ASIC	Hard
of_eth_mac_100g	40G/50G/100G Ethernet MAC and PCS	planned	FPGA + ASIC	Very hard
of_eth_mac_400g	200G/400G Ethernet MAC and PCS	planned	FPGA + ASIC	Very hard
of_eth_mac_800g	800G Ethernet MAC and PCS	planned	FPGA + ASIC	Very hard

ethernet_pcs

3 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_eth_sgmii_pcs	SGMII / 1000BASE-X PCS	planned	FPGA + ASIC	Medium
of_eth_usxgmii	USXGMII multi-rate PCS	planned	FPGA + ASIC	Medium
of_eth_flexe	FlexE shim	planned	FPGA + ASIC	Very hard

ethernet_offload

7 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_eth_ptp_tsu	IEEE 1588 PTP timestamping unit	simulated	FPGA + ASIC	Medium
of_udp_ip_offload	UDP/IPv4 offload engine	planned	FPGA + ASIC	Medium
of_tcp_offload	TCP offload engine	planned	FPGA + ASIC	Very hard
of_roce_v2	RoCE v2 RDMA engine	planned	FPGA + ASIC	Very hard
of_uet_transport	Ultra Ethernet transport engine	planned	FPGA + ASIC	Very hard
of_macsec_framer	MACsec SecTAG framer	planned	FPGA + ASIC	Hard
of_ncsi	NC-SI sideband controller	planned	FPGA + ASIC	Medium

ethernet_switch

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_eth_l2_switch	Layer-2 Ethernet switch	planned	FPGA + ASIC	Hard

pcie

7 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_pcie_g3_ctrl	PCIe Gen3 controller (EP/RP)	planned	FPGA + ASIC	Hard
of_pcie_g4_ctrl	PCIe Gen4 controller (EP/RP)	planned	FPGA + ASIC	Very hard
of_pcie_g5_ctrl	PCIe Gen5 controller (EP/RP)	planned	FPGA + ASIC	Very hard
of_pcie_g6_ctrl	PCIe Gen6 controller (EP/RP)	planned	FPGA + ASIC	Very hard
of_pcie_g7_ctrl	PCIe Gen7 controller (EP/RP)	planned	FPGA + ASIC	Very hard
of_pcie_switch	PCIe switch	planned	FPGA + ASIC	Very hard
of_pcie_dma	PCIe multi-channel DMA engine	planned	FPGA + ASIC	Hard

cxl

5 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cxl11_dev	CXL 1.1 device controller	planned	FPGA + ASIC	Very hard
of_cxl2_type3	CXL 2.0 Type 3 memory expander controller	planned	FPGA + ASIC	Very hard
of_cxl3_dev	CXL 3.x device controller	planned	FPGA + ASIC	Very hard
of_cxl_root_port	CXL host root port	planned	FPGA + ASIC	Very hard
of_ccix	CCIX transaction and link layer	planned	FPGA + ASIC	Very hard

usb

9 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_usb_fs_device	USB 2.0 full-speed device	simulated	FPGA + ASIC	Medium
of_usb2_device	USB 2.0 high-speed device controller	planned	FPGA + ASIC	Medium
of_usb2_host	USB 2.0 host controller (EHCI/OHCI)	planned	FPGA + ASIC	Hard
of_usb2_otg	USB 2.0 OTG dual-role controller	planned	FPGA + ASIC	Hard
of_usb3_device	USB 3.2 device controller	planned	FPGA + ASIC	Hard
of_usb3_xhci	USB 3.2 xHCI host controller	planned	FPGA + ASIC	Very hard
of_usb3_drd	USB 3.2 dual-role controller	planned	FPGA + ASIC	Very hard
of_usb4_router	USB4 router	planned	FPGA + ASIC	Very hard
of_typec_pd	USB Type-C and Power Delivery controller	planned	FPGA + ASIC	Medium

display

11 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_hdmi21_tx	HDMI 2.1 transmitter controller	planned	FPGA + ASIC	Very hard
of_hdmi21_rx	HDMI 2.1 receiver controller	planned	FPGA + ASIC	Very hard
of_dp14_tx	DisplayPort 1.4 source controller	planned	FPGA + ASIC	Hard
of_dp14_rx	DisplayPort 1.4 sink controller	planned	FPGA + ASIC	Hard
of_dp21_tx	DisplayPort 2.1 source controller	planned	FPGA + ASIC	Very hard
of_edp_tx	eDP 1.5 transmitter controller	planned	FPGA + ASIC	Hard
of_dsi2_host	MIPI DSI-2 host controller	planned	FPGA + ASIC	Hard
of_dsi_device	MIPI DSI peripheral receiver	planned	FPGA + ASIC	Hard
of_lvds_disp_tx	LVDS display transmitter (OpenLDI)	planned	FPGA + ASIC	Easy
of_vbyone_tx	V-by-One HS transmitter controller	planned	FPGA + ASIC	Medium
of_parallel_video_out	Parallel RGB / BT.656 / BT.1120 video output	planned	FPGA + ASIC	Easy

camera

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_csi2_rx	MIPI CSI-2 receiver	planned	FPGA + ASIC	Hard
of_csi2_tx	MIPI CSI-2 transmitter	planned	FPGA + ASIC	Medium
of_slvs_ec_rx	SLVS-EC link layer receiver	planned	FPGA + ASIC	Hard
of_dvp_camera	Parallel camera interface (DVP)	planned	FPGA + ASIC	Easy

die_to_die

5 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_ucie_adapter	UCIe die-to-die adapter	planned	FPGA + ASIC	Very hard
of_ucie_axi_bridge	AXI over UCIe streaming bridge	planned	FPGA + ASIC	Hard
of_bow_link	BoW die-to-die link layer	planned	FPGA + ASIC	Hard
of_aib_adapter	AIB adapter	planned	FPGA + ASIC	Hard
of_openhbi_link	OpenHBI link layer	planned	FPGA + ASIC	Hard

debug

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cjtag	Compact JTAG (IEEE 1149.7) adapter	planned	FPGA + ASIC	Medium
of_swd_dp	Serial Wire Debug port	planned	FPGA + ASIC	Medium

converter_link

3 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_jesd204b	JESD204B link layer	planned	FPGA + ASIC	Hard
of_jesd204c	JESD204C link layer	planned	FPGA + ASIC	Hard
of_jesd204d	JESD204D link layer	planned	FPGA + ASIC	Very hard

serdes_protocol

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_aurora_link	Aurora-compatible lightweight link	planned	FPGA + ASIC	Medium
of_interlaken	Interlaken controller	planned	FPGA + ASIC	Very hard
of_spi42	SPI-4.2 interface	planned	FPGA + ASIC	Medium
of_srio	Serial RapidIO endpoint	planned	FPGA + ASIC	Hard

fronthaul

3 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpri	CPRI link controller	planned	FPGA + ASIC	Hard
of_ecpri	eCPRI framer	planned	FPGA + ASIC	Medium
of_oran_fh	O-RAN fronthaul C/U-plane engine	planned	FPGA + ASIC	Hard

wireless_mac

3 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_802154_mac	IEEE 802.15.4 MAC accelerator	planned	FPGA + ASIC	Medium
of_ble_ll	Bluetooth LE link layer	planned	FPGA + ASIC	Hard
of_wifi_mac_helper	Wi-Fi lower-MAC assist	planned	FPGA + ASIC	Hard

space_avionics

5 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_spacewire	SpaceWire codec and router port	planned	FPGA + ASIC	Medium
of_spacefibre	SpaceFibre interface	planned	FPGA + ASIC	Hard
of_mil1553	MIL-STD-1553B controller	planned	FPGA + ASIC	Medium
of_arinc429	ARINC 429 transceiver controller	planned	FPGA + ASIC	Easy
of_afdx_es	AFDX (ARINC 664 Part 7) end system	planned	FPGA + ASIC	Hard

smart_card

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_iso7816	ISO 7816 smart card interface	planned	FPGA + ASIC	Easy

management

3 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_mdio	MDIO management master	simulated	FPGA + ASIC	Easy
of_espi	eSPI controller and target	planned	FPGA + ASIC	Medium
of_lpc	LPC bus host and peripheral	planned	FPGA + ASIC	Easy

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