IP PortfolioCompute accelerators
Compute accelerators: AI, GPU, TPU and HPC
Neural network accelerators, systolic arrays, GPU shader and raster blocks, tensor units, sparse and graph engines, database and network offload, scientific computing engines.
Blocks 93Implemented 9Families 8ASIC (CMOS) only 5 · FPGA + ASIC 88
npu
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_acc_systolic_gemm | Systolic GEMM array | planned | FPGA + ASIC | Hard |
| of_acc_tpu_mxu | TPU-style matrix unit | planned | FPGA + ASIC | Very hard |
| of_acc_conv_engine | Convolution engine | planned | FPGA + ASIC | Hard |
| of_acc_depthwise_conv | Depthwise and pointwise convolution unit | planned | FPGA + ASIC | Medium |
| of_acc_winograd_conv | Winograd convolution engine | planned | FPGA + ASIC | Hard |
| of_acc_attention | Transformer attention engine | planned | FPGA + ASIC | Very hard |
| of_acc_kv_cache_mgr | KV cache manager | planned | FPGA + ASIC | Hard |
| of_acc_softmax | Softmax unit | simulated | FPGA + ASIC | Medium |
| of_acc_norm_unit | LayerNorm and RMSNorm unit | simulated | FPGA + ASIC | Medium |
| of_acc_activation | Activation function unit | simulated | FPGA + ASIC | Easy |
| of_acc_quantizer | Quantise and dequantise unit | simulated | FPGA + ASIC | Medium |
| of_acc_mx_dot | Microscaling dot-product unit | planned | FPGA + ASIC | Hard |
| of_acc_sparse_tensor | Sparse tensor engine | planned | FPGA + ASIC | Very hard |
| of_acc_edge_npu | Edge NPU | planned | FPGA + ASIC | Hard |
| of_acc_npu_tile | Datacenter NPU tile | planned | FPGA + ASIC | Very hard |
| of_acc_npu_vector | NPU vector processor | planned | FPGA + ASIC | Hard |
| of_acc_tensor_dma | Tensor DMA engine | simulated | FPGA + ASIC | Medium |
| of_acc_embedding | Embedding lookup engine | planned | FPGA + ASIC | Medium |
| of_acc_moe_router | Mixture-of-experts router | planned | FPGA + ASIC | Hard |
| of_acc_token_sampler | LLM token sampler | planned | FPGA + ASIC | Medium |
| of_acc_bnn | Binary and ternary network engine | planned | FPGA + ASIC | Medium |
| of_acc_rnn | Recurrent network engine | planned | FPGA + ASIC | Medium |
| of_acc_ssm_scan | State-space model scan engine | planned | FPGA + ASIC | Hard |
| of_acc_kws | Keyword spotting accelerator | planned | FPGA + ASIC | Medium |
| of_acc_audio_features | Audio feature extractor | planned | FPGA + ASIC | Medium |
| of_acc_weight_decomp | Weight decompression unit | planned | FPGA + ASIC | Medium |
| of_acc_collective | Collective communication engine | planned | FPGA + ASIC | Hard |
| of_acc_nms | Detection post-processing engine | planned | FPGA + ASIC | Medium |
| of_acc_nn_preproc | Neural network input preprocessor | planned | FPGA + ASIC | Medium |
gpu
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_acc_gpu_simt_core | SIMT shader core | planned | FPGA + ASIC | Very hard |
| of_acc_gpu_tensor_core | GPU tensor core | planned | FPGA + ASIC | Hard |
| of_acc_gpu_cmd_proc | GPU command processor | planned | FPGA + ASIC | Hard |
| of_acc_gpu_geometry | Geometry front end | planned | FPGA + ASIC | Hard |
| of_acc_gpu_rasterizer | Rasteriser | planned | FPGA + ASIC | Hard |
| of_acc_gpu_texture | Texture unit | planned | FPGA + ASIC | Hard |
| of_acc_gpu_rop | Render output unit | planned | FPGA + ASIC | Hard |
| of_acc_gpu_tbdr | Tile-based rendering binner | planned | FPGA + ASIC | Very hard |
| of_acc_gpu_compute | Compute-only GPU cluster | planned | FPGA + ASIC | Very hard |
| of_acc_gpu_raytrace | Ray tracing BVH unit | planned | FPGA + ASIC | Very hard |
| of_acc_gpu_2d | 2D graphics and blitter engine | planned | FPGA + ASIC | Medium |
| of_acc_display_compositor | Display compositor | planned | FPGA + ASIC | Hard |
| of_acc_gpu_memsys | GPU memory subsystem | planned | FPGA + ASIC | Very hard |
hpc
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_acc_fft | Streaming FFT engine | simulated | FPGA + ASIC | Medium |
| of_acc_blas | BLAS engine | planned | FPGA + ASIC | Hard |
| of_acc_spmv_graph | Sparse matrix and graph engine | planned | FPGA + ASIC | Hard |
| of_acc_stencil | Stencil computation engine | planned | FPGA + ASIC | Medium |
| of_acc_md_forces | Molecular dynamics force pipeline | planned | FPGA + ASIC | Hard |
| of_acc_monte_carlo | Monte Carlo engine | planned | FPGA + ASIC | Medium |
| of_acc_seq_align | Sequence alignment engine | planned | FPGA + ASIC | Medium |
| of_acc_matrix_decomp | Matrix decomposition engine | planned | FPGA + ASIC | Hard |
| of_acc_sort | Sorting engine | planned | FPGA + ASIC | Medium |
| of_acc_ising | Digital annealer | planned | FPGA + ASIC | Hard |
| of_acc_cgra | Coarse-grained reconfigurable array | planned | FPGA + ASIC | Very hard |
| of_acc_efpga | Embedded FPGA fabric | planned | ASIC (CMOS) only | Very hard |
data_offload
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_acc_deflate_comp | DEFLATE compressor | planned | FPGA + ASIC | Hard |
| of_acc_deflate_decomp | DEFLATE decompressor | planned | FPGA + ASIC | Medium |
| of_acc_zstd | Zstandard codec | planned | FPGA + ASIC | Hard |
| of_acc_lz4_snappy | LZ4 and Snappy codec | planned | FPGA + ASIC | Medium |
| of_acc_regex | Regular expression and DPI engine | planned | FPGA + ASIC | Hard |
| of_acc_pkt_parser | Programmable packet parser | planned | FPGA + ASIC | Hard |
| of_acc_match_action | Match-action pipeline stage | planned | FPGA + ASIC | Very hard |
| of_acc_hash_table | Hash table lookup engine | simulated | FPGA + ASIC | Medium |
| of_acc_traffic_mgr | Traffic manager | planned | FPGA + ASIC | Hard |
| of_acc_ebpf | eBPF packet processor | planned | FPGA + ASIC | Hard |
| of_acc_toe | TCP offload engine | planned | FPGA + ASIC | Very hard |
| of_acc_rdma | RDMA engine | planned | FPGA + ASIC | Very hard |
| of_acc_csum_offload | Checksum and CRC offload | simulated | FPGA + ASIC | Easy |
| of_acc_db_filter | Database scan and filter engine | planned | FPGA + ASIC | Medium |
| of_acc_db_join | Hash join and aggregation engine | planned | FPGA + ASIC | Hard |
| of_acc_columnar_decode | Columnar format decoder | planned | FPGA + ASIC | Medium |
| of_acc_json_parse | JSON and CSV parser | planned | FPGA + ASIC | Medium |
| of_acc_erasure | Erasure coding engine | simulated | FPGA + ASIC | Medium |
| of_acc_dedup | Deduplication chunking engine | planned | FPGA + ASIC | Medium |
| of_acc_video_me | Video motion estimation engine | planned | FPGA + ASIC | Hard |
| of_acc_video_entropy | Video entropy coding engine | planned | FPGA + ASIC | Hard |
signal
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_acc_beamformer | Digital beamformer | planned | FPGA + ASIC | Hard |
| of_acc_correlator | FX correlator | planned | FPGA + ASIC | Hard |
| of_acc_channelizer | Polyphase channeliser | planned | FPGA + ASIC | Medium |
| of_acc_radar_proc | Radar range-Doppler and CFAR engine | planned | FPGA + ASIC | Hard |
| of_acc_ldpc | LDPC decoder | planned | FPGA + ASIC | Hard |
| of_acc_kalman | Kalman filter engine | planned | FPGA + ASIC | Medium |
| of_acc_cv_features | Vision feature extraction engine | planned | FPGA + ASIC | Medium |
| of_acc_stereo | Stereo disparity engine | planned | FPGA + ASIC | Hard |
| of_acc_pointcloud | Point cloud processing engine | planned | FPGA + ASIC | Hard |
| of_acc_polar | Polar decoder | planned | FPGA + ASIC | Hard |
neuromorphic
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_acc_snn_core | Spiking neuron core | planned | FPGA + ASIC | Hard |
| of_acc_snn_router | Spike event router | planned | FPGA + ASIC | Medium |
in_memory
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_acc_cim_sram_digital | Digital SRAM compute-in-memory macro | planned | ASIC (CMOS) only | Very hard |
| of_acc_cim_sram_analog | Analog SRAM compute-in-memory macro | planned | ASIC (CMOS) only | Very hard |
| of_acc_cim_nvm | Resistive crossbar compute-in-memory macro | planned | ASIC (CMOS) only | Very hard |
| of_acc_near_memory | Near-memory processing unit | planned | FPGA + ASIC | Hard |
photonic
| ID | Block | Maturity | Targets | Difficulty |
|---|---|---|---|---|
| of_acc_photonic_ctrl | Photonic compute mesh controller | planned | FPGA + ASIC | Hard |
| of_acc_photonic_afe | Photonic compute analog front end | planned | ASIC (CMOS) only | Very hard |