Technology
Virtual silicon before you pay for silicon
A respin costs months and a mask set. Our goal is to simulate as much as physics allows before any FPGA board or tapeout, with every layer calibrated against measured data. Simulation cuts respins. It does not remove silicon, because errors stack across layers and some effects only show on a real die. We say that in the tool, not only here.
fpga-routed 26Blocks at simulated 245Blocks planned 1,139Maturity tiers
Maturity is earned, one reproducible flow at a time
Every IP block carries a tier, stored with the evidence that produced it. A block moves up only when the flow for the next tier runs clean and anyone can rerun it. The new tiers between formal and fpga are the virtual tapeout.
planned · 1,139Catalog entry with interfacesskeletonLint-clean register skeletonsimulated · 245Self-checking testbench vs a referenceformalProperties provenfpga-routed · 26Timing met on a routed FPGA netlistsignoffDRC, LVS, STA clean per PDKfpgaRunning on a boardsiliconMeasured on a shuttle chip| Tier | Earned when | Risk still open |
|---|---|---|
| simulated | Lint clean under Verilator, a self-checking testbench passes against a bit-exact Python reference model, with official vectors where they exist | Synthesis, timing, real clocks and I/O |
| formal | Properties for the block type proven with SymbiYosys | Physical implementation |
| fpga-routed | Yosys and nextpnr route the block for ECP5, iCE40 or Gowin, timing met at a stated clock, and the block's own testbench passes on the routed netlist with FPGA cell models | Board-level clocks, I/O standards and power |
| signoff | RTL to GDS per open PDK, DRC and LVS clean, timing met at ss, tt and ff, power and IR reported, gate-level simulation with SDF at each corner | Silicon variability and unmodelled physics |
| signoff-ams | Extracted-parasitic SPICE with Monte Carlo over corners, yield stated in percent | Silicon variability and unmodelled physics |
| silicon | Measured on a fabricated chip, such as a multi-project shuttle test die | Volume yield and qualification |
The simulation chain
From atoms to the assembled product
Each layer hands calibrated results to the one above it. The left column is what ships today. The right column is what we are building next.
Factory
TodayDiscrete-event fab simulation and robot cells
NextA digital twin of a production line
System
TodayVerilator co-simulation with firmware, Renode and QEMU
NextEmulation-scale runs
Package and board
TodayPackage thermal and warpage, SI/PI, multiphysics
NextCoupled electro-thermal-mechanical runs, turbulence and radiation
Analog and mixed signal
Todayngspice and Xyce
NextMonte Carlo yield in the signoff-ams tier
Post-layout simulation
TodayIcarus Verilog and Verilator
NextThe same testbench on the gate netlist with SDF at each corner
Digital signoff
TodayOpenROAD flow, multi-corner OpenSTA, power and IR, DRC, LVS, PEX
NextThe virtual tapeout signoff tier for every block
Standard cells
TodayCharacterisation with ngspice into Liberty
NextCells for compound-semiconductor processes
Device
TodayDEVSIM device simulation
NextCompact-model extraction feeding SPICE
Process
TodayProcess steps, ViennaPS topography, lithography, epitaxy and bonding
NextCalibration to measured wafers
Materials and chemistry
TodayMaterial properties database (pymatgen)
NextCantera kinetics for CVD, etch and ALD; atomistic and band-structure codes
Engineering choices
What makes the results trustworthy
Models you can audit
Every model cites its correlation or standard and states its validity range: Deal-Grove and Massoud oxidation, IEEE 1241 and 1139 for spectrum analysis, IEC 61000-4-7 and IEEE 1459 for power. Placeholders and assumptions are labelled in the interface.
Native DRC, LVS and extraction in Rust
openforge-drc, openforge-lvs and openforge-xrc use R-tree spatial indexing, VF2 graph matching with device folding, and fringe and coupling capacitance models, with a lookup-table mode for foundry RC data.
From the boule up
Crystal growth (Cz, MCz and FZ for silicon; LEC and VGF for GaAs and InP), epitaxy, implant, diffusion, oxidation, lithography and bonding feed DEVSIM device simulation and compact model cards.
One project, chip to enclosure
Ball maps flow into PCB fanout, power maps flow into conjugate heat transfer, and boards flow into enclosures through ECAD to MCAD exchange, without re-entering data.
Autotuned flows
Flow parameters can be searched with Bayesian optimisation across runs, and an optional local language model assists inside the app without sending designs off the machine.
Evidence stored with the block
Engines run at pinned versions and each block keeps the results that earned its tier next to its sources, so anyone can rerun the flow and compare.
Results
Example chips in the repository
Each example ships with its configuration, sources and a signoff report, so these numbers can be reproduced. They are open-PDK results, not foundry signoff.
| Example | PDK | Cells | Outcome |
|---|---|---|---|
asic-picorv32-sky130 RISC-V CPU | sky130A | 7,971 | RTL to GDS, LVS match 7,971 / 7,971, extracted 14.5 nF typical |
asic-caravel-mgmt-sky130 management SoC | sky130A | 22,151 | RTL to GDS, 113 MB GDS, extracted 69.3 nF typical |
asic-caravel-sky130 Wishbone counter | sky130A | 268 | LVS match 315 / 315 |
asic-counter-ihp-sg13g2 | IHP SG13G2 | 33 | 0 detail-route DRC violations, LVS match 38 / 38 |
asic-counter-sky130 | sky130A | 35 | Full RTL to GDS, LVS match 35 / 35 |
How we label what we know
These rules apply to the product, the documentation and this site.
A planned block is a plan. A simulated block has passed simulation and nothing more. Tiers only move with evidence.
When a value has no source it is marked as a placeholder or an assumption in the results, with a count of how many a result depends on.
Cryptographic blocks are constant time by design and are not certified. Reliability and safety bundles produce evidence, not approvals.
Models are calibrated against measured test structures. Variability, defects and new-process physics still need silicon to confirm.
Calibrate it against your process
Foundries and labs with test structure data can help close the loop between simulation and silicon.
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