IP PortfolioCompute acceleratorsnpu
of_acc_activation
Activation function unit
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Piecewise polynomial and lookup-table evaluator for GELU, SiLU, sigmoid, tanh, exp and reciprocal square root with configurable accuracy.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| x_in | in | AXI4-Stream | 256 | |
| y_out | out | AXI4-Stream | 256 |
Standards
No external standard applies.
More in npu
| ID | Block | Maturity |
|---|---|---|
| of_acc_systolic_gemm | Systolic GEMM array | planned |
| of_acc_tpu_mxu | TPU-style matrix unit | planned |
| of_acc_conv_engine | Convolution engine | planned |
| of_acc_depthwise_conv | Depthwise and pointwise convolution unit | planned |
| of_acc_winograd_conv | Winograd convolution engine | planned |
| of_acc_attention | Transformer attention engine | planned |
| of_acc_kv_cache_mgr | KV cache manager | planned |
| of_acc_softmax | Softmax unit | simulated |
| of_acc_norm_unit | LayerNorm and RMSNorm unit | simulated |
| of_acc_quantizer | Quantise and dequantise unit | simulated |