IP PortfolioCompute acceleratorsgpu
of_acc_gpu_tensor_core
GPU tensor core
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Warp-level matrix multiply-accumulate unit inside the SIMT core for FP16, BF16, INT8 and FP8 operands.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- IEEE 754-2019
- OCP 8-bit Floating Point Specification (OFP8)
More in gpu
| ID | Block | Maturity |
|---|---|---|
| of_acc_gpu_simt_core | SIMT shader core | planned |
| of_acc_gpu_cmd_proc | GPU command processor | planned |
| of_acc_gpu_geometry | Geometry front end | planned |
| of_acc_gpu_rasterizer | Rasteriser | planned |
| of_acc_gpu_texture | Texture unit | planned |
| of_acc_gpu_rop | Render output unit | planned |
| of_acc_gpu_tbdr | Tile-based rendering binner | planned |
| of_acc_gpu_compute | Compute-only GPU cluster | planned |
| of_acc_gpu_raytrace | Ray tracing BVH unit | planned |
| of_acc_gpu_2d | 2D graphics and blitter engine | planned |