IP PortfolioAnalog and mixed-signaliii_v
of_ams_iiiv_hbt_comparator
InP HBT ultra-fast comparator
Maturity plannedTargets III-V processDifficulty HardPriority 2
ECL/CML latched comparator in InP HBT technology for multi-GHz flash ADCs and timing circuits.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| vinp | inout | analog | 1 | |
| vinn | inout | analog | 1 | |
| clkin | in | differential pair | 1 | |
| qout | out | differential pair | 1 |
Standards
No external standard applies.
Notes
For Dyber, Inc. in-house InP HBT process.
More in iii_v
| ID | Block | Maturity |
|---|---|---|
| of_ams_iiiv_hbt_bandgap | InP HBT bandgap reference | planned |
| of_ams_iiiv_hbt_dac | InP HBT high-speed DAC | planned |
| of_ams_iiiv_hbt_th | InP HBT track-and-hold amplifier | planned |
| of_ams_iiiv_hbt_vco | InP HBT millimeter-wave VCO | planned |
| of_ams_iiiv_hbt_divider | InP HBT static frequency divider | planned |
| of_ams_iiiv_hbt_driver | InP HBT optical modulator driver | planned |
| of_ams_iiiv_tia_pin | InP/InGaAs photoreceiver TIA | planned |
| of_ams_iiiv_phemt_opamp | GaAs pHEMT wideband amplifier | planned |
| of_ams_iiiv_phemt_bias | GaAs pHEMT bias and sequencing controller | planned |
| of_ams_iiiv_ed_logic | GaAs E/D-mode logic and level translator | planned |