IP PortfolioAnalog and mixed-signalisolation_hv
of_ams_iso_digital
Capacitive digital galvanic isolator
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 2
On-off keyed or edge-based transmitter and receiver across an on-chip or in-package capacitive barrier for digital isolation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| din | in | parallel | 4 | |
| barrier | inout | analog | 8 | |
| dout | out | parallel | 4 |
Standards
- IEC 60747-17
- UL 1577
More in isolation_hv
| ID | Block | Maturity |
|---|---|---|
| of_ams_iso_power | Isolated power transfer driver | planned |
| of_ams_hv_level_shifter | High-voltage level shifter | planned |
| of_ams_io_hv_tolerant | High-voltage tolerant analog switch | planned |