IP PortfolioDatapath and DSPdsp filters
of_iir_biquad
IIR biquad cascade
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Cascade of second-order IIR sections in direct form I or transposed direct form II with coefficient reload, scaling and saturation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| s_in | in | AXI4-Stream | 32 | |
| m_out | out | AXI4-Stream | 32 |
Standards
No external standard applies.
More in dsp filters
| ID | Block | Maturity |
|---|---|---|
| of_fir | FIR filter | simulated |
| of_fir_polyphase | Polyphase decimator and interpolator | simulated |
| of_cic | CIC decimator and interpolator | simulated |
| of_halfband | Half-band filter | planned |
| of_farrow | Fractional resampler (Farrow) | planned |
| of_lms | Adaptive LMS / NLMS filter | planned |