IP PortfolioDatapath and DSPbit manipulation
of_lzc
Leading-zero / leading-one counter
Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1
Log-depth leading-zero (or leading-one) counter; count == WIDTH when the word is all zeros (ones).
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| a | in | parallel | 32 | |
| cnt | out | parallel | 6 |
Standards
No external standard applies.
More in bit manipulation
| ID | Block | Maturity |
|---|---|---|
| of_popcount | Population count | simulated |
| of_prienc | Priority encoder | simulated |
| of_shifter | Barrel shifter / rotator | simulated |
| of_bitrev | Bit, byte and nibble reverse / swap | planned |
| of_bitmanip_rv | RISC-V bit-manipulation unit | planned |
| of_clmul | Carry-less multiplier | planned |