IP PortfolioPhysical IPdie marking, alignment and finishing
of_chip_id_rom
Metal-programmable chip ID cell
Maturity plannedTargets ASIC (CMOS) onlyDifficulty EasyPriority 1
Tie-cell based ID register whose value is set by a single metal or via layer, so mask revisions update the readable chip revision.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| id_out | out | parallel | 32 |
Standards
No external standard applies.
More in die marking, alignment and finishing
| ID | Block | Maturity |
|---|---|---|
| of_seal_ring | Seal ring | planned |
| of_align_marks | Lithography alignment and overlay marks | planned |
| of_die_mark | Die marking and logo cells | planned |
| of_fill_gen | Density fill generator | planned |