IP PortfolioPhysical IPspecial-purpose cells
of_sc_dual_rail
Dual-rail precharge logic cells
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 3
Balanced dual-rail and sense-amplifier based logic cells with matched rail capacitance for side-channel resistant datapaths.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- Liberty
More in special-purpose cells
| ID | Block | Maturity |
|---|---|---|
| of_sc_retention | State-retention flip-flops | planned |
| of_sc_level_shift | Level shifter cells | planned |
| of_sc_isolation | Isolation cells | planned |
| of_sc_aon | Always-on buffers and inverters | planned |
| of_sc_power_switch | Header and footer power switch cells | planned |
| of_sc_icg | Integrated clock gating cells | planned |
| of_sc_clock | Clock tree cells | planned |
| of_sc_sync | Synchronizer flip-flop cells | planned |
| of_sc_mbff | Multi-bit flip-flops | planned |
| of_sc_async | Asynchronous logic cells | planned |