IP PortfolioInterface controllersdram
of_ddr5_mrdimm_ctrl
DDR5 MRDIMM host controller
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
DDR5 host controller for multiplexed-rank DIMMs that issues pseudo-channel commands through the MRCD and data buffers to double module bandwidth over an RDIMM channel.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| host | in | AXI4-Stream | 512 | |
| dfi | out | parallel | 1024 | |
| dfi_rd | in | valid-qualified bus | 512 |
Standards
- JEDEC JESD79-5
Notes
Host side for the Dyber, Inc. III-V memory bridge (DDR5/MRDIMM attach). Cite the JEDEC MRDIMM module and MRCD standards once published.
More in dram
| ID | Block | Maturity |
|---|---|---|
| of_ddr3_ctrl | DDR3/DDR3L memory controller | planned |
| of_ddr4_ctrl | DDR4 memory controller | planned |
| of_ddr5_ctrl | DDR5 memory controller | planned |
| of_lpddr4_ctrl | LPDDR4/LPDDR4X memory controller | planned |
| of_lpddr5_ctrl | LPDDR5/LPDDR5X memory controller | planned |
| of_lpddr6_ctrl | LPDDR6 memory controller | planned |
| of_gddr6_ctrl | GDDR6 memory controller | planned |
| of_gddr7_ctrl | GDDR7 memory controller | planned |