IP PortfolioInterface controllersserdes_protocol
of_interlaken
Interlaken controller
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
Interlaken packet interface with 64b/67b framing, channelisation, burst interleaving, in-band and out-of-band flow control across bonded lanes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| phy_tx | out | parallel | 1024 | |
| phy_rx | in | parallel | 1024 | |
| tx | in | AXI4-Stream | 512 | |
| rx | out | AXI4-Stream | 512 |
Standards
- Interlaken Protocol Definition Revision 1.2
More in serdes_protocol
| ID | Block | Maturity |
|---|---|---|
| of_aurora_link | Aurora-compatible lightweight link | planned |
| of_spi42 | SPI-4.2 interface | planned |
| of_srio | Serial RapidIO endpoint | planned |