IP PortfolioInterface controllerssmart_card
of_iso7816
ISO 7816 smart card interface
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 3
Smart card reader interface for T=0 and T=1 protocols with ATR handling, ETU timing, guard time, parity error retransmission and card clock generation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| sc_clk | out | clock | 1 | |
| sc_io | inout | serial | 1 | |
| sc_rst | out | serial | 1 |
Standards
- ISO/IEC 7816-3