of_tsn_qbv

Time-aware shaper (802.1Qbv)

Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2

Per-port gate control list engine for 8 traffic classes with gPTP-synchronised cycle start, guard bands and admin/oper list switch-over.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
tx_in	in	AXI4-Stream	64
tx_out	out	AXI4-Stream	64

Standards

IEEE 802.1Qbv-2015
IEEE 802.1Q-2022

More in tsn

ID	Block	Maturity
of_tsn_gptp	gPTP time synchronisation unit	simulated
of_tsn_qbu	Frame preemption (802.1Qbu/802.3br)	planned
of_tsn_frer	Frame replication and elimination (802.1CB)	planned
of_tsn_switch	TSN Ethernet switch	planned