IP PortfolioInterface controllersuart
of_uart
UART with APB interface
Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1
Asynchronous serial port with programmable baud divisor, 5 to 8 data bits, parity, 1 or 2 stop bits, TX/RX FIFOs and error detection.
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| txd | out | serial | 1 | |
| rxd | in | serial | 1 |
Standards
No external standard applies.
More in uart
| ID | Block | Maturity |
|---|---|---|
| of_uart_16550 | 16550-compatible UART | simulated |
| of_usart | USART with RS-485 and IrDA SIR | planned |