IP PortfolioInterface controllersdie_to_die
of_ucie_axi_bridge
AXI over UCIe streaming bridge
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Bridge that carries AXI4 read and write channels over the UCIe streaming protocol with credit-based flow control and ordering rules.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| fdi_tx | out | AXI4-Stream | 512 | |
| fdi_rx | in | AXI4-Stream | 512 |
Standards
- UCIe 2.0
- AMBA AXI4
More in die_to_die
| ID | Block | Maturity |
|---|---|---|
| of_ucie_adapter | UCIe die-to-die adapter | planned |
| of_bow_link | BoW die-to-die link layer | planned |
| of_aib_adapter | AIB adapter | planned |
| of_openhbi_link | OpenHBI link layer | planned |