IP PortfolioInterface controllersusb
of_usb_fs_device
USB 2.0 full-speed device
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
USB 2.0 full-speed (12 Mbit/s) device controller with on-chip transceiver interface, endpoint buffer memory and SOF-based clock trimming.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| usb_dp | inout | serial | 1 | |
| usb_dn | inout | serial | 1 | |
| usb_oe | out | serial | 1 |
Standards
- USB 2.0
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in usb
| ID | Block | Maturity |
|---|---|---|
| of_usb2_device | USB 2.0 high-speed device controller | planned |
| of_usb2_host | USB 2.0 host controller (EHCI/OHCI) | planned |
| of_usb2_otg | USB 2.0 OTG dual-role controller | planned |
| of_usb3_device | USB 3.2 device controller | planned |
| of_usb3_xhci | USB 3.2 xHCI host controller | planned |
| of_usb3_drd | USB 3.2 dual-role controller | planned |
| of_usb4_router | USB4 router | planned |
| of_typec_pd | USB Type-C and Power Delivery controller | planned |