IP PortfolioInterface PHYshigh_speed
of_inp_hbt_cdr
InP DHBT clock and data recovery retimer
Maturity plannedTargets III-V processDifficulty Very hardPriority 2
Clock and data recovery and retiming stage in InP DHBT for very high symbol-rate optical links, with phase detector, loop filter interface and recovered-clock output.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| din | in | differential pair | 1 | |
| dout | out | differential pair | 1 | |
| rclk | out | differential pair | 1 |
Standards
No external standard applies.
More in high_speed
| ID | Block | Maturity |
|---|---|---|
| of_inp_hbt_mux_demux | InP DHBT 2:1 selector and 1:2 demultiplexer | planned |