IP PortfolioInterface PHYsconverter_phy
of_jesd204c_phy
JESD204C SerDes PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
JESD204B/C SerDes lanes up to 32 Gb/s with deterministic-latency clocking, SYSREF capture and lane-to-lane alignment for RF data converters.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | differential pair | 8 | |
| rx | in | differential pair | 8 | |
| refclk | in | differential pair | 1 | |
| pma_tx | in | parallel | 512 | |
| pma_rx | out | parallel | 512 | |
| sysref | in | differential pair | 1 |
Standards
- JEDEC JESD204C
- JEDEC JESD204B