IP PortfolioInterface PHYsdisplay_phy
of_vbyone_phy
V-by-One HS transmitter PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 3
Embedded-clock CML transmitter PHY up to 4 Gb/s per lane for V-by-One HS panel links with pre-emphasis.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| lane | out | differential pair | 8 | |
| par_tx | in | parallel | 80 | |
| refclk | in | clock | 1 |
Standards
No external standard applies.
Notes
V-by-One HS is a THine Electronics specification.
More in display_phy
| ID | Block | Maturity |
|---|---|---|
| of_hdmi20_tx_phy | HDMI 2.0 TMDS transmitter PHY | planned |
| of_hdmi21_tx_phy | HDMI 2.1 transmitter PHY | planned |
| of_hdmi21_rx_phy | HDMI 2.1 receiver PHY | planned |
| of_dp14_tx_phy | DisplayPort 1.4 / eDP transmitter PHY | planned |
| of_dp21_tx_phy | DisplayPort 2.1 transmitter PHY | planned |
| of_dp_rx_phy | DisplayPort receiver PHY | planned |