IP PortfolioVideo, imaging and audiodisplay
of_mm_disp_hdr_meta
HDR metadata processor
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Parses and generates static and dynamic HDR metadata and applies PQ and HLG transfer functions with tone mapping to the target display.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pix_in | in | AXI4-Stream | 30 | |
| pix_out | out | AXI4-Stream | 30 |
Standards
- SMPTE ST 2084
- SMPTE ST 2086
- SMPTE ST 2094-40
- ITU-R BT.2100
- CTA-861-H
More in display
| ID | Block | Maturity |
|---|---|---|
| of_mm_disp_ctrl | Display controller | planned |
| of_mm_disp_compositor | Hardware compositor | planned |
| of_mm_disp_frc | Frame rate converter | planned |
| of_mm_disp_dsc_enc | VESA DSC encoder | planned |
| of_mm_disp_dsc_dec | VESA DSC decoder | planned |
| of_mm_disp_tcon | Panel timing controller (TCON) | planned |
| of_mm_disp_overdrive | LCD overdrive | planned |
| of_mm_disp_local_dimming | Local dimming controller | planned |
| of_mm_disp_oled_comp | OLED compensation and burn-in mitigation | planned |
| of_mm_disp_gamut | Display gamut mapping and 3D LUT | planned |