IP PortfolioVideo, imaging and audiographics_2d
of_mm_gfx_blitter
2D blitter
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 1
DMA-driven rectangle copy, fill, colour format conversion and raster operations between surfaces in memory.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| src | in | AXI4-Stream | 64 | |
| dst | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in graphics_2d
| ID | Block | Maturity |
|---|---|---|
| of_mm_gfx_alpha_blend | Alpha blending engine | planned |
| of_mm_gfx_rotate | Image rotation and mirroring | planned |
| of_mm_gfx_font | Font and glyph renderer | planned |
| of_mm_gfx_vector | 2D vector graphics rasterizer | planned |
| of_mm_gfx_fbc | Frame buffer compression | planned |