IP PortfolioVideo, imaging and audioisp

of_mm_isp_dpc

Defect pixel correction

Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1

Static defect map and dynamic hot and dead pixel detection with neighbourhood-based replacement on raw Bayer streams.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAPB control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
raw_ininAXI4-Stream16 
raw_outoutAXI4-Stream16 

Standards

No external standard applies.

More in isp

IDBlockMaturity
of_mm_isp_blcBlack level correctionsimulated
of_mm_isp_lscLens shading correctionsimulated
of_mm_isp_demosaicBayer demosaicsimulated
of_mm_isp_3a_statsAuto exposure, white balance and focus statisticssimulated
of_mm_isp_awb_gainWhite balance gain and colour correction matrixsimulated
of_mm_isp_gammaGamma and tone curve LUTsimulated
of_mm_isp_hdr_mergeMulti-exposure HDR mergeplanned
of_mm_isp_tonemapLocal tone mappingplanned
of_mm_isp_nr2dSpatial noise reductionsimulated
of_mm_isp_nr3dTemporal noise reductionplanned