IP PortfolioVideo, imaging and audiovideo_codec
of_mm_vid_h264_enc
H.264/AVC encoder
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
Hardware H.264 encoder with intra and inter prediction, motion estimation, rate control and CAVLC and CABAC entropy coding.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pix_in | in | AXI4-Stream | 30 | |
| bitstream | out | AXI4-Stream | 64 |
Standards
- ITU-T H.264
More in video_codec
| ID | Block | Maturity |
|---|---|---|
| of_mm_vid_h264_dec | H.264/AVC decoder | planned |
| of_mm_vid_h265_enc | H.265/HEVC encoder | planned |
| of_mm_vid_h265_dec | H.265/HEVC decoder | planned |
| of_mm_vid_h266_dec | H.266/VVC decoder | planned |
| of_mm_vid_h266_enc | H.266/VVC encoder | planned |
| of_mm_vid_vp9_dec | VP9 decoder | planned |
| of_mm_vid_vp9_enc | VP9 encoder | planned |
| of_mm_vid_av1_dec | AV1 decoder | planned |
| of_mm_vid_av1_enc | AV1 encoder | planned |
| of_mm_vid_jpeg | JPEG encoder and decoder | planned |