IP PortfolioVideo, imaging and audioxr

of_mm_xr_passthrough

Video passthrough processor

Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3

Low-latency camera-to-display path with reprojection to eye position, distortion correction and blending with rendered content.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAXI4-Lite control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
caminAXI4-Stream30 
renderinAXI4-Stream32 
pix_outoutAXI4-Stream30 

Standards

No external standard applies.

More in xr

IDBlockMaturity
of_mm_xr_timewarpAsynchronous time warp engineplanned
of_mm_xr_foveationFoveated rendering helperplanned
of_mm_xr_eye_trackEye tracking image front endplanned