IP PortfolioCompute acceleratorssignal
of_acc_cv_features
Vision feature extraction engine
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Image pyramid, FAST corner detection, orientation and binary descriptor computation for visual odometry and SLAM.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pix_in | in | AXI4-Stream | 64 | |
| feat_out | out | AXI4-Stream | 128 |
Standards
No external standard applies.
More in signal
| ID | Block | Maturity |
|---|---|---|
| of_acc_beamformer | Digital beamformer | planned |
| of_acc_correlator | FX correlator | planned |
| of_acc_channelizer | Polyphase channeliser | planned |
| of_acc_radar_proc | Radar range-Doppler and CFAR engine | planned |
| of_acc_ldpc | LDPC decoder | planned |
| of_acc_kalman | Kalman filter engine | planned |
| of_acc_stereo | Stereo disparity engine | planned |
| of_acc_pointcloud | Point cloud processing engine | planned |
| of_acc_polar | Polar decoder | planned |