IP PortfolioCompute acceleratorsdata_offload
of_acc_erasure
Erasure coding engine
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Reed-Solomon encode and decode over GF(2^8) for k+m layouts including RAID-6 P and Q parity.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| blk_in | in | AXI4-Stream | 512 | |
| par_out | out | AXI4-Stream | 512 |
Standards
No external standard applies.
More in data_offload
| ID | Block | Maturity |
|---|---|---|
| of_acc_deflate_comp | DEFLATE compressor | planned |
| of_acc_deflate_decomp | DEFLATE decompressor | planned |
| of_acc_zstd | Zstandard codec | planned |
| of_acc_lz4_snappy | LZ4 and Snappy codec | planned |
| of_acc_regex | Regular expression and DPI engine | planned |
| of_acc_pkt_parser | Programmable packet parser | planned |
| of_acc_match_action | Match-action pipeline stage | planned |
| of_acc_hash_table | Hash table lookup engine | simulated |
| of_acc_traffic_mgr | Traffic manager | planned |
| of_acc_ebpf | eBPF packet processor | planned |