IP PortfolioAnalog and mixed-signalclocking

of_ams_cdr

Clock and data recovery

Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2

Bang-bang (Alexander) phase detector CDR with phase interpolator that extracts a clock from an NRZ serial stream for SerDes receivers.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAPB control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
rxdindifferential pair1 
refclkinclock1 
rclkoutclock1 
rdataoutparallel16 

Standards

No external standard applies.

More in clocking

IDBlockMaturity
of_ams_pll_intnInteger-N charge-pump PLLplanned
of_ams_pll_fracnFractional-N PLL with delta-sigma modulatorplanned
of_ams_adpllAll-digital PLLplanned
of_ams_vco_ringRing voltage-controlled oscillatorplanned
of_ams_vco_lcLC voltage-controlled oscillatorplanned
of_ams_dllDelay-locked loopplanned
of_ams_xoCrystal oscillator driverplanned
of_ams_xo_32k32.768 kHz low-power crystal oscillatorplanned
of_ams_rcoscTrimmed RC oscillatorplanned
of_ams_ssc_genSpread-spectrum clock modulatorplanned