IP PortfolioAnalog and mixed-signalclocking
of_ams_dll
Delay-locked loop
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 2
Voltage-controlled delay line locked to one reference period, producing multiple equally spaced clock phases for DDR and source-synchronous interfaces.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| refclk | in | clock | 1 | |
| phases | out | clock | 8 | |
| lock | out | serial | 1 |
Standards
- JEDEC JESD79-5
More in clocking
| ID | Block | Maturity |
|---|---|---|
| of_ams_pll_intn | Integer-N charge-pump PLL | planned |
| of_ams_pll_fracn | Fractional-N PLL with delta-sigma modulator | planned |
| of_ams_adpll | All-digital PLL | planned |
| of_ams_vco_ring | Ring voltage-controlled oscillator | planned |
| of_ams_vco_lc | LC voltage-controlled oscillator | planned |
| of_ams_cdr | Clock and data recovery | planned |
| of_ams_xo | Crystal oscillator driver | planned |
| of_ams_xo_32k | 32.768 kHz low-power crystal oscillator | planned |
| of_ams_rcosc | Trimmed RC oscillator | planned |
| of_ams_ssc_gen | Spread-spectrum clock modulator | planned |