IP PortfolioAnalog and mixed-signaldata_converters
of_ams_dac_cs
Current-steering DAC
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 2
Segmented unary and binary current-source DAC with dynamic element matching for high-speed waveform generation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| codes | in | AXI4-Stream | 16 | |
| ioutp | inout | analog | 1 | |
| ioutn | inout | analog | 1 |
Standards
- JEDEC JESD204C
More in data_converters
| ID | Block | Maturity |
|---|---|---|
| of_ams_adc_sar | SAR ADC | planned |
| of_ams_adc_sar_hr | High-resolution SAR ADC with calibration | planned |
| of_ams_adc_pipeline | Pipelined ADC | planned |
| of_ams_adc_sd_audio | Audio delta-sigma ADC | planned |
| of_ams_adc_sd_precision | Precision delta-sigma ADC | planned |
| of_ams_adc_ti_rf | Time-interleaved RF-sampling ADC | planned |
| of_ams_adc_flash | Flash ADC | planned |
| of_ams_adc_incremental | Incremental ADC | planned |
| of_ams_adc_vco | VCO-based ADC | planned |
| of_ams_adc_housekeeping | Housekeeping ADC with input mux | planned |