IP PortfolioAnalog and mixed-signaldata_converters
of_ams_dac_r2r
R-2R ladder DAC
Maturity plannedTargets ASIC (CMOS) onlyDifficulty MediumPriority 1
Voltage-mode R-2R resistor ladder DAC with output buffer for trimming, bias setting and slow waveform output.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| code | in | parallel | 12 | |
| vout | inout | analog | 1 |
Standards
No external standard applies.
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| ID | Block | Maturity |
|---|---|---|
| of_ams_adc_sar | SAR ADC | planned |
| of_ams_adc_sar_hr | High-resolution SAR ADC with calibration | planned |
| of_ams_adc_pipeline | Pipelined ADC | planned |
| of_ams_adc_sd_audio | Audio delta-sigma ADC | planned |
| of_ams_adc_sd_precision | Precision delta-sigma ADC | planned |
| of_ams_adc_ti_rf | Time-interleaved RF-sampling ADC | planned |
| of_ams_adc_flash | Flash ADC | planned |
| of_ams_adc_incremental | Incremental ADC | planned |
| of_ams_adc_vco | VCO-based ADC | planned |
| of_ams_adc_housekeeping | Housekeeping ADC with input mux | planned |