IP PortfolioAnalog and mixed-signalpower_management
of_ams_pwr_seq
Power sequencer
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Programmable state machine that enables rails in order, waits for power-good, and sequences shutdown and fault responses.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pgood | in | parallel | 16 | |
| rail_en | out | parallel | 16 |
Standards
- PMBus 1.3
More in power_management
| ID | Block | Maturity |
|---|---|---|
| of_ams_ldo | General-purpose LDO regulator | planned |
| of_ams_ldo_capless | Capacitor-less LDO | planned |
| of_ams_ldo_lownoise | Low-noise LDO for RF and clock supplies | planned |
| of_ams_ldo_digital | Digital LDO | planned |
| of_ams_ldo_hv | High-voltage input LDO | planned |
| of_ams_buck | Synchronous buck converter | planned |
| of_ams_buck_multiphase | Multiphase buck controller | planned |
| of_ams_boost | Boost converter | planned |
| of_ams_buck_boost | Four-switch buck-boost converter | planned |
| of_ams_dcdc_sc | Switched-capacitor DC-DC converter | planned |