IP PortfolioDatapath and DSPdsp signal processing
of_cmul
Complex multiplier
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Complex multiply with three-multiplier or four-multiplier structure, optional conjugate, rounding and saturation, pipelined.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| a | in | AXI4-Stream | 32 | |
| b | in | AXI4-Stream | 32 | |
| m_out | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in dsp signal processing
| ID | Block | Maturity |
|---|---|---|
| of_mixer | Digital complex mixer | planned |
| of_ddc | Digital down-converter | planned |
| of_duc | Digital up-converter | planned |
| of_correlator | Multi-lag correlator | planned |
| of_matched_filter | Matched filter and pulse compressor | planned |
| of_agc | Digital automatic gain control | planned |