IP PortfolioDatapath and DSPinteger arithmetic
of_csa_tree
Carry-save adder tree (Wallace / Dadda)
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Multi-operand carry-save adder tree of 3:2 compressors reducing N_IN operands to a sum/carry pair (sum + carry == sum of inputs mod 2^WIDTH). ARCH selects Wallace (greedy) or Dadda (lazy, sequence 2,3,4,6,9,13,...) stage scheduling.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ops | in | parallel | 256 | |
| sum | out | parallel | 64 |
Standards
No external standard applies.
More in integer arithmetic
| ID | Block | Maturity |
|---|---|---|
| of_add_ripple | Ripple-carry adder | simulated |
| of_add_cla | Carry-lookahead adder | simulated |
| of_add_csel | Carry-select adder | simulated |
| of_add_kogge_stone | Kogge-Stone parallel-prefix adder | fpga-routed |
| of_add_brent_kung | Brent-Kung parallel-prefix adder | simulated |
| of_add_sklansky | Sklansky parallel-prefix adder | simulated |
| of_addsub | Adder/subtractor with flags | simulated |
| of_inc | Incrementer / decrementer | simulated |
| of_abs | Absolute value | simulated |
| of_cmp | Magnitude comparator | simulated |