IP PortfolioDatapath and DSPerror control coding
of_ecc_dec
Hamming / SECDED decoder
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Decoder/corrector for of_ecc_enc codewords: corrects single-bit errors and (SECDED) detects double-bit errors; reports the syndrome.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| code | in | parallel | 72 | |
| m_out | out | parallel | 64 |
Standards
No external standard applies.
More in error control coding
| ID | Block | Maturity |
|---|---|---|
| of_crc | Parallel CRC | fpga-routed |
| of_ecc_enc | Hamming / SECDED encoder | simulated |
| of_parity | Parity generator and checker | planned |
| of_bch_codec | BCH encoder and decoder | planned |
| of_rs_codec | Reed-Solomon encoder and decoder | planned |
| of_ldpc_dec | LDPC encoder and decoder | planned |
| of_polar_codec | Polar encoder and list decoder | planned |
| of_turbo_dec | Turbo encoder and decoder | planned |
| of_viterbi | Convolutional encoder and Viterbi decoder | planned |
| of_ecc_symbol | Symbol-based memory ECC (single symbol correct) | planned |