IP PortfolioDatapath and DSPerror control coding
of_ldpc_dec
LDPC encoder and decoder
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Quasi-cyclic LDPC encoder and layered min-sum decoder with run-time loadable base matrices and early termination; supports 5G NR base graphs and Wi-Fi codes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| llr | in | AXI4-Stream | 128 | |
| m_out | out | AXI4-Stream | 64 |
Standards
- 3GPP TS 38.212
- IEEE 802.11
More in error control coding
| ID | Block | Maturity |
|---|---|---|
| of_crc | Parallel CRC | fpga-routed |
| of_ecc_enc | Hamming / SECDED encoder | simulated |
| of_ecc_dec | Hamming / SECDED decoder | simulated |
| of_parity | Parity generator and checker | planned |
| of_bch_codec | BCH encoder and decoder | planned |
| of_rs_codec | Reed-Solomon encoder and decoder | planned |
| of_polar_codec | Polar encoder and list decoder | planned |
| of_turbo_dec | Turbo encoder and decoder | planned |
| of_viterbi | Convolutional encoder and Viterbi decoder | planned |
| of_ecc_symbol | Symbol-based memory ECC (single symbol correct) | planned |