IP PortfolioDatapath and DSPdsp transforms and oscillators
of_fft_mem
Memory-based mixed-radix FFT
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
In-place memory-based FFT/IFFT with radix-2/4 and split-radix butterflies, non-power-of-two sizes via prime-factor stages, and conflict-free bank addressing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| s_in | in | AXI4-Stream | 32 | |
| m_out | out | AXI4-Stream | 32 |
Standards
No external standard applies.
More in dsp transforms and oscillators
| ID | Block | Maturity |
|---|---|---|
| of_fft_stream | Streaming pipelined FFT/IFFT | planned |
| of_cordic | CORDIC rotator and vectoring unit | fpga-routed |
| of_nco | NCO / direct digital synthesizer | simulated |
| of_window | Window function generator | planned |
| of_dct | 2D DCT / IDCT | planned |