IP PortfolioDatapath and DSPfloating point
of_fp_add
Floating-point adder/subtractor
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
IEEE 754 adder/subtractor for any binary format (default binary32/single precision) with round-to-nearest-even, full subnormal support and exception flags.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| a | in | parallel | 32 | |
| b | in | parallel | 32 | |
| y | out | parallel | 32 |
Standards
- IEEE 754-2019
More in floating point
| ID | Block | Maturity |
|---|---|---|
| of_fp_mul | Floating-point multiplier | simulated |
| of_fp_round | Floating-point round & pack unit | simulated |
| of_fp2int | Floating-point to fixed-point converter | simulated |
| of_int2fp | Fixed-point to floating-point converter | simulated |
| of_fp_fma | Floating-point fused multiply-add | simulated |
| of_fp_divsqrt | Floating-point divide and square root | simulated |
| of_fp_cmp | Floating-point compare, min/max and classify | simulated |
| of_fp_cvt | Floating-point format converter | simulated |
| of_bf16_dotp | bfloat16 dot-product unit | simulated |
| of_fp8_mac | FP8 (E4M3 / E5M2) multiply-accumulate | simulated |