IP PortfolioDatapath and DSPfloating point
of_fp_divsqrt
Floating-point divide and square root
Maturity simulatedTargets FPGA + ASICDifficulty HardPriority 1
IEEE 754 division and square root for binary32 and binary64 using an iterative digit-recurrence datapath with correct rounding in all modes and exception flags.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| opnd | in | valid-qualified bus | 64 | |
| y | out | valid-qualified bus | 32 |
Standards
- IEEE 754-2019
Basis projects
Permissive open projects the implementation may build on.
- OpenHW Group CVFPU (FPnew) (SHL-0.51)
- Berkeley HardFloat (BSD-3-Clause)
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|---|---|---|
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