IP PortfolioDatapath and DSPinteger arithmetic
of_int_alu
Integer ALU
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Parametric integer ALU with add, subtract, logic, shifts, set-less-than and compare-for-branch operations matching the RISC-V RV32I/RV64I base integer set.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| opnd | in | parallel | 128 | |
| y | out | parallel | 64 |
Standards
- RISC-V Unprivileged ISA 20191213
More in integer arithmetic
| ID | Block | Maturity |
|---|---|---|
| of_add_ripple | Ripple-carry adder | simulated |
| of_add_cla | Carry-lookahead adder | simulated |
| of_add_csel | Carry-select adder | simulated |
| of_add_kogge_stone | Kogge-Stone parallel-prefix adder | fpga-routed |
| of_add_brent_kung | Brent-Kung parallel-prefix adder | simulated |
| of_add_sklansky | Sklansky parallel-prefix adder | simulated |
| of_addsub | Adder/subtractor with flags | simulated |
| of_inc | Incrementer / decrementer | simulated |
| of_abs | Absolute value | simulated |
| of_cmp | Magnitude comparator | simulated |