IP PortfolioDatapath and DSPmatrix and linear algebra
of_mat_inv
Matrix inversion unit
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Small-matrix inversion (up to 16x16) by Gauss-Jordan elimination with partial pivoting or via QR, for MIMO detection and beamforming.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| s_in | in | AXI4-Stream | 64 | |
| m_out | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in matrix and linear algebra
| ID | Block | Maturity |
|---|---|---|
| of_systolic_mm | Systolic matrix multiply array | planned |
| of_transpose | Matrix transpose and corner-turn buffer | planned |
| of_qr_givens | QR decomposition (Givens rotations) | planned |
| of_cholesky | Cholesky decomposition and solver | planned |