IP PortfolioDatapath and DSPmatrix and linear algebra
of_systolic_mm
Systolic matrix multiply array
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Output- or weight-stationary systolic array of MAC cells for integer, bfloat16 or FP8 GEMM, with operand skew buffers and accumulator drain.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| a_in | in | AXI4-Stream | 256 | |
| b_in | in | AXI4-Stream | 256 | |
| c_out | out | AXI4-Stream | 512 |
Standards
No external standard applies.
More in matrix and linear algebra
| ID | Block | Maturity |
|---|---|---|
| of_transpose | Matrix transpose and corner-turn buffer | planned |
| of_qr_givens | QR decomposition (Givens rotations) | planned |
| of_cholesky | Cholesky decomposition and solver | planned |
| of_mat_inv | Matrix inversion unit | planned |