IP PortfolioDatapath and DSPnumber theory
of_mod_addsub
Modular adder and subtractor
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Computes (a +/- b) mod m for run-time or constant modulus with single conditional correction; parametric width up to 4096 bits.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| opnd | in | valid-qualified bus | 512 | |
| y | out | valid-qualified bus | 256 |
Standards
No external standard applies.
More in number theory
| ID | Block | Maturity |
|---|---|---|
| of_mont_mul | Montgomery modular multiplier | planned |
| of_barrett_red | Barrett modular reducer | planned |
| of_ntt_butterfly | Number-theoretic transform butterfly and engine | planned |