IP PortfolioDatapath and DSPinteger arithmetic

of_mul_booth4

Radix-4 Booth multiplier

Maturity fpga-routedTargets FPGA + ASICDifficulty MediumPriority 1

Radix-4 modified-Booth recoded multiplier: ceil((B_WIDTH+1)/2) partial products from {0, +-a, +-2a}, Dadda reduction, one carry-propagate adder.

FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.

Interfaces

PortDirectionKindWidthNotes
ainparallel32 
binparallel32 
poutparallel64 

Standards

No external standard applies.

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