IP PortfolioDatapath and DSPinteger arithmetic
of_mul_pipe
Pipelined multiplier
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Pipelined multiplier with valid tracking and clock enable: Booth or AND partial products, Dadda tree, registers after the carry-save tree and the final adder; extra stages are appended at the output for retiming.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| opnd | in | valid-qualified bus | 64 | |
| prod | out | valid-qualified bus | 64 |
Standards
No external standard applies.
More in integer arithmetic
| ID | Block | Maturity |
|---|---|---|
| of_add_ripple | Ripple-carry adder | simulated |
| of_add_cla | Carry-lookahead adder | simulated |
| of_add_csel | Carry-select adder | simulated |
| of_add_kogge_stone | Kogge-Stone parallel-prefix adder | fpga-routed |
| of_add_brent_kung | Brent-Kung parallel-prefix adder | simulated |
| of_add_sklansky | Sklansky parallel-prefix adder | simulated |
| of_addsub | Adder/subtractor with flags | simulated |
| of_inc | Incrementer / decrementer | simulated |
| of_abs | Absolute value | simulated |
| of_cmp | Magnitude comparator | simulated |