IP PortfolioDatapath and DSPcontrol and scheduling
of_pwm
Multi-channel PWM generator
Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1
N-channel pulse-width modulator with a shared W-bit counter, edge- or center-aligned modes, double-buffered period / duty / polarity (glitch-free updates), registered outputs and a period-start strobe.
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| pwm | out | parallel | 8 |
Standards
No external standard applies.
More in control and scheduling
| ID | Block | Maturity |
|---|---|---|
| of_cnt_updown | Up/down counter | simulated |
| of_cnt_gray | Gray-code counter | simulated |
| of_cnt_johnson | Johnson counter | simulated |
| of_arb_fixed | Fixed-priority arbiter | simulated |
| of_arb_rr | Round-robin arbiter | fpga-routed |
| of_arb_wrr | Weighted round-robin arbiter | simulated |
| of_arb_matrix | Matrix (least-recently-granted) arbiter | simulated |
| of_credit_cnt | Credit counter | simulated |
| of_debounce | Debouncer | simulated |
| of_edge_detect | Edge detector | simulated |