IP PortfolioDatapath and DSPrandom number generation
of_lfsr
LFSR (Fibonacci / Galois)
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Maximal-length linear-feedback shift register in Fibonacci or Galois form with a built-in primitive-polynomial tap table for widths 2..64 (or user taps), load and enable.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| q | out | parallel | 32 |
Standards
No external standard applies.
More in random number generation
| ID | Block | Maturity |
|---|---|---|
| of_prbs | PRBS generator and checker | simulated |
| of_xoshiro | xoshiro / xoroshiro PRNG | planned |
| of_awgn | Gaussian noise generator | planned |